 |
|
|
|
RTC-4543SA/SB
|
|
|
|
| |
| DC characteristic |
|
Output voltage (VOL)
|
| Q |
The Output voltage (VOL) on
DC characteristic is regulated as 5 V=GND+0.5 V Max. and 3 V=GND+0.8 V
Max.. The maximum of 5 V is lower than that of 3 V. Is this correct? |
| A |
That's correct.
 |
The VOL specification regulates the characteristic
of increasing GND potential at the lower voltage side when assuming
a high load (a load current of 1mA).
If a load current is about 100  A,
it actually has the potential of GND+0.1V. So, please check
the value of VOL in the specification along with current condition
at the connected side. |
|
|
Consumption current
|
| Q |
Is it possible for consumption
current to increase by several dozen A
depending on how it's used? Further, is it possible to face a similar
situation if we have any malfunction modes? |
| A |
Depending on conditions for
using the module, reasons for increased current may be the following:
1) There is a terminal in which penetration current is generated under
the open state during backup.
2) A clock signal is output while the FOUT terminal is connected to
a large load.
3) Current is leaked from the real time clock module to others.
In case of a malfunction mode, current may be leaked due to electrostatic
destruction. |
|
 |
| |
| Timing operation |
|
Indicating nonexistent date
|
| Q |
The data shows nonexistent dates
such as January 32. |
| A |
The data form is mistaken and
be using.
|
The data is a BCD code. Please delimit the read
data every 4 bits and relate them to the 10th digit and 1st
digit. |
|
|
Timing malfunction
|
| Q |
What are some potential causes
of clock data being destroyed? |
| A |
An internal function does not
clear data by itself.
One possible cause is the unexpected lowering of VDD voltage in a
short amount of time.
Like other electrical devices, this can be caused by an electric short
of the power supply or a terminal, and by the entry of high voltage
such as static electricity. |
|
|
| |
| Initial setting |
|
Internal state when initially
activating power
|
| Q |
Are there any default values
in internal data when power is initially activated? |
| A |
There is not a default value.
|
The state of all internal registers when initially
activating power becomes indeterminate except the FDT bits.
Please initialize all registers except the FDT bit prior to
use. |
|
|
FDT bit
|
| Q |
Is the FDT bit "0"
or "1" when power is initially activated? |
| A |
FDT bit is becomes "1".
|
The bit for detecting a power source voltage (FDT
bit) becomes "1" when the power is initially activated
(raised from 0V to VDD or returning from a level at or below
backup voltage.) |
|
|
Internal state when initially
activating power
|
| Q |
How many seconds does it take
to set the time and calendar register after initially activating power?
|
| A |
It takes three seconds according to the
specifications.
|
Time is needed to start oscillation of the internal
quartz resonator. It takes three seconds according to the specifications,
but oscillation can actually start within 1 second. |
|
|
|
| |
| Processing terminals |
|
| |
| Setting register |
|
TM bit
|
| Q |
The TEST bit is forcibly turned
"ON", but it returns to the "OFF state" soon after.
Is the TEST state temporary, and is it safe to assume there is no
current increase that could affect the backup battery? |
| A |
The test condition is temporary.
Also, there is the increase of a current.
|
The TEST bit changes its function depending on
combination of other bits, which can cause a significant current
increase. Please take care that the TEST bit is always a zero
cleared state and not set by an error operation. Details of
the TEST function are not disclosed. |
|
|
FDT bit
|
| Q |
The FDT bit becomes "1"
even though there is no drop in voltage supply.
Can the FDT bit become "1" when the voltage supply is normal? |
| A |
The FDT bit is not set when
you use the module under conditions within a guaranteed range.
|
The malfunction could be caused by applying a
higher voltage to the I/O terminal than that of the power supply.
Be aware that exceeding the absolute maximum conditions, even
temporarily, can destroy the module. |
|
|
|
| |
| Time and calendar |
|
Calendar function
|
| Q |
How does the week digit set
by the week counter operate?
What happens if the week register is set to zero or a number over
seven? |
| A |
The day of week data becomes
indeterminate.
|
Week data in this module is numerical data from
one to seven and is counted up every time the date is renewed.
It cycles between the 7 numbers, one for each day of the week.
Values of zero and over seven do not exist, so the day of week
data becomes indeterminate. It does not, however, affect other
registers. |
|
|
Calendar function
|
| Q |
Does it matter what the week
digit data is set to (e.g.- zero) if it is not used for operation
of the calendar? |
| A |
No problem.
|
If you do not use the week digit register, its
value does not affect other timing and calendar functions. Please
ignore the week digit data when reading data. |
|
|
|
| |
| Access operation (READ/WRITE) |
|
Effect of lowering power source
to internal data in Real Time Clock Module
|
| Q |
What happens to the data if
the power voltage drops below the standard value for the clock? |
| A |
Stored data become indeterminate
and a meaningless value. |
|
Interrupting communication
|
| Q |
Is it possible for clock data
to be destroyed if the CE and WR terminals become LOW before inputting
52 bits when writing data to the module. Otherwise, can the previous
clock data be hold? |
| A |
The data may be destroyed.
|
The logic is designed to prevent changing anything
other than the "*-bit" and year digit bit may have changed at the time when broke an access to Real Time Clock Module.please perform re-write of data to these bits if necessary.As for the other clock data,it is not changed by an access interruption. |
|
|
|
| |
| Timer interrupting function |
|
| |
| Others |
|
| |
 |
