Condtion1. If quartz oscillation is temporarily stopped for any reason, the fos bit is set.
If quartz oscillation cannot be maintained by lowering a source voltage, the fos bit is set. The internal quartz runs with a minimum of 1.6 V, so the fos bit is set when voltage is under 1.6 V.

Condition 2. If the power on reset circuit is operated, it is set.
The reset circuit may be operated unintentionally due to a rapid fluctuation of power voltage or glitch. If a fos bit malfunction is suspected, check if the conditions described in "Sect. 8: Switch to backup and recovery" of the application manual are satisfied.

Condition 3. When the power voltage of the real time clock is lowered to the backup potential and an interface is driven by normal potential, the voltage of the interface becomes higher than the power voltage of the real time clock and may surpass the absolute maximum standard (ABS) for input voltage of the real time clock. In such case, values of not only the fos bit, but also internal registers bits may be changed.
The accepted range, which des not affect reliability and real time clock module error operation due to overshooting and under shooting, is Vcc/Vss 1 V and under 10 ns.

Condition 4. "1" can be written to the fos bit.
If access timing that resets the fos bit to "1" happens to be generated during a signal change such as switching a power source, "1" is written to the fos bit. Accidentally writing "1" will not affect other functions, but should not be done intentionally.