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RTC-4574SA/JENB,RX-4574LC,RX-4575SG,RA-4574SA
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| DC characteristic |
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| Timing operation |
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Reading data using the HOLD
function
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| Q |
When the main power source of
a system is turned on and time is read out a little while after the
main power is turned off, timing is suspended and the time at turning
the main power off is left without change. What are the potential
causes? |
| A |
It is related to the HOLD function.
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If a main power source is turned off under the
state of HOLD"1", timing is suspended during the time
since a carry is not performed.
Please turn the power source off after certainly setting the
HOLD bit clear "0".
We recommend you to "use the fr bit and read it out"
if you can not control timing of turning a power source off. |
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| Initial setting |
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Internal state when activating
power
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| Q |
What is the state of time data
(date, time, calendars and bits for various settings) when the initial
power source is activated? |
| A |
All data bits are indeterminate.
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All data bits are indeterminate (floating) when
a power is activated (however, the fos bit is "1").
Be sure to initialize the bits. |
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| Processing terminals |
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Processing an input terminal
during backup
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| Q |
Can input terminals be floating
during backup, or do they need to be fixed at some level? |
| A |
Terminals can be floating (indeterminate)
without problem only during backup.
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But, please be aware of the following:
1) We recommend that the CEO terminal be opened (or "L"
level.)
2) The CE1 and FCON terminals are floating only when the FE
bit is "0".
3) Make sure that an input terminal does not become an intermediate
potential. |
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Processing an input terminal
under normal operation
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| Q |
Can input terminals be floating
other than during backup if they are not being accessed, or do they
need to be fixed at some level? |
| A |
Floating is prohibited.
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Floating is prohibited under normal operation
whether you access the module or not.
Please fix the terminal to be "H" or "L".
(However, the DATA terminal can be floating.) |
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Processing /AIRQ and /TIRQ terminals
under normal operation
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| Q |
/AIRQ and /TIRQ terminals are
open drain output. How do we use them? |
| A |
Please pull each terminal up
with a resister.
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/AIRQ and /TIRQ terminals are N-ch open drain.
But, an interrupt output signal for each terminal is output
as active "L".
This output requires pull-up processing.
*Pull-up processing is needed when using timing functions during
backup. This processing is not needed when you do not use timing
functions. |
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Processing /AIRQ and /TIRQ terminals
under normal operation
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| Q |
Can /AIRQ and /TIRQ terminals
be pulled up to a potential higher than the VDD potential? |
| A |
/AIRQ and /TIRQ terminals can
be pulled up to +6.0 V regardless of the VDD potential. |
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Processing the DATA terminal
under normal operation
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| Q |
Does the DATA terminal need
pull-up or other processing? |
| A |
It is not necessary.
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Do not install pull up or pull down resisters
on the terminal unless there are specific design reasons. |
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| Setting register |
| Canceling
the HOLD bit |
| Q |
Is the HOLD bit "1"
automatically cancelled? |
| A |
The HOLD bit "1" is
not automatically cancelled.
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You must write a "0" (zero clearing)
to cancel the HOLD bit. |
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Operating condition of "fos
bit"
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| Q |
Under what condition is the
fos bit set to "1"? |
| A |
The fos bit is set under the
following 4 conditions:
Condtion1.
If quartz oscillation is temporarily stopped for any
reason, the fos bit is set.
If quartz oscillation cannot be maintained by lowering a source
voltage, the fos bit is set. The internal quartz runs with a minimum
of 1.6 V, so the fos bit is set when voltage is under 1.6 V.
Condition 2.
If the power on reset circuit is operated, it is set.
The reset circuit may be operated unintentionally due to a rapid
fluctuation of power voltage or glitch. If a fos bit malfunction
is suspected, check if the conditions described in "Sect. 8:
Switch to backup and recovery" of the application manual are
satisfied.
Condition 3.
When the power voltage of the real time clock is lowered
to the backup potential and an interface is driven by normal potential,
the voltage of the interface becomes higher than the power voltage
of the real time clock and may surpass the absolute maximum standard
(ABS) for input voltage of the real time clock. In such case, values
of not only the fos bit, but also internal registers bits may be
changed.
The accepted range, which des not affect reliability and real time
clock module error
operation due to overshooting and under shooting, is Vcc/Vss  1 V
and under 10 ns.
Condition 4.
"1" can be written to the fos bit.
If access timing that resets the fos bit to "1" happens
to be generated during a signal change such as switching a power
source, "1" is written to the fos bit. Accidentally writing
"1" will not affect other functions, but should not be
done intentionally.
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| Time and calendar |
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Setting time
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| Q |
Are there any ways to accurately
set the time? |
| A |
Accurately setting the time
involves initializing (resetting) the internal sub-second counter.
Setting the RESET bit to "1" resets the internal counter.
Please set the RESET and STOP bits to "1" prior to actually
setting the time, and then cancel the STOP bit (return to "0")
when you want to start the clock. (The RESET bit is automatically
cancelled.) |
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| Access operation (READ/WRITE) |
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Operation without meeting AC
regulations
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| Q |
What happens when a module is
accessed without satisfying the AC regulation? |
| A |
The modules cannot be correctly
accessed if out of regulation.
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There is also the possibility of adverse effects
such as increasing consumption current.
Please contact us when using a module outside the regulation
voltage. |
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| Timer interrupting function |
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| Others |
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